Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 247
9.4.2.6 eMIOS200 UC B Register (EMIOSB[n])
Depending on the mode of operation, internal registers B1 or B2 can be assigned to address EMIOSB[n].
Both B1 and B2 are cleared by reset. Table 9-14 summarizes the EMIOSB[n] read and write accesses for
all operation modes. For more information, see section Section 9.5.1.1, UC modes of operation.
Depending on the channel configuration, it may or may not have the EMIOSB register. The EMIOSB
register is required for the following modes: OPWMB, OPWFMB, and MCB.
Address: UC[n] base address + 0x04 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
B
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-13. eMIOS200 UC B register (EMIOSB[n])
Table 9-14. EMIOSA[n], EMIOSB[n], and EMIOSALTA[n] value assignments
Mode of operation
Register access
Write Read Write Read Alt write Alt read
GPIO A1, A2 A1 B1, B2 B1 A2 A2
SAIC
1
— A2 B2 B2 — —
SAOC
1
1
In these modes, the EMIOSB[n] register is not used, but B2 can be accessed.
A2 A1 B2 B2 — —
MCB
1
A2 A1 B2 B2 — —
OPWFMB A2 A1 B2 B1 — —
OPWMB A2 A1 B2 B1 — —
To Next Page
Loading...
