Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
226 Freescale Semiconductor
8.10.4.1 Crystal clock monitor
If FOSC is smaller than FRCfast divided by 2
RCDIV
bits of CMU_CSR and the CK_FXOSC is ‘ON’ as
signaled by the MC_ME, then:
• An event pending bit, OLRI in CMU_ISR, is set.
• A failure event OLR is signaled to the MC_RGM, which in turn can automatically switch to a safe
fallback clock and generate an interrupt or a reset.
8.10.4.2 PLL clock monitor
The PLL clock CK_PLL frequency can be monitored by programming the CME bit of the CMU_CSR
register to 1. CK_PLL monitor starts as soon as CME bit is set. This monitor can be disabled at any time
by writing a 0 to the CME bit.
If CK_PLL frequency (FPLL) is greater than a reference value determined by the HFREF[11:0] bits of
CMU_HFREFR and the CK_PLL is ‘ON’ as signaled by the MC_ME, then:
• An event pending bit FHHI in CMU_ISR is set.
• A failure event is signaled to the MC_RGM and Fault Collection Unit, which in turn can generate
an interrupt or a reset.
If FPLL is less than a reference clock frequency (FRC/4) and the CK_PLL is ‘ON’ as signaled by the
MC_ME, then the event pending bit FLCI in CMU_ISR will be set.
If FPLL is less than a reference value determined by the LFREF[11:0] bits of CMU_LFREFR and the
CK_PLL is ‘ON’ as signaled by the MC_ME, then:
• An event pending bit FLLI in CMU_ISR is set.
• A failure event FLL is signaled to the MC_RGM, which can generate an interrupt or a reset.
NOTE
The on-chip RC oscillator is used as the reliable reference clock for the
clock supervision. In order to avoid false events, proper programming of the
dividers is required. These have to take into account the accuracy and
frequency deviation of the RC oscillator.
8.10.4.3 Frequency meter
The purpose of the frequency meter is to calibrate the internal RC oscillator (CK_IRC) using a known
frequency.
Hint: This value can then be stored in the flash memory so that application software can reuse it later.
The reference clock is always the FXOSC. The frequency meter returns a precise value of CK_32K,
CK_FIRC, or CK_SIRC, according to the value of the CKSEL1 bit. The measurement starts when SFM
(Start Frequency Measure) bit in CMU_CSR is set to 1. The CMU_MDR register gives the measurement
duration in number of clock cycles of the selected clock source, with a width of 20 bits. The SFM bit is
reset to 0 by the hardware once the frequency measurement is done and the count is loaded in the
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