NXP Semiconductors MPC5606S - Motor Controller Control Register 0 (MCCTL0)

Stepper Motor Controller (SMC)
MPC5606S Microcontroller Reference Manual, Rev. 7
1126 Freescale Semiconductor
35.3.2.1 Motor Controller Control Register 0 (MCCTL0)
This register controls the operating mode of the SMC module.
.
rwm A read/write bit that may be modified by hardware in some fashion other than by a reset.
w1c Write one to clear. A flag bit that can be read, is cleared by writing a one, writing 0 has no effect.
Reset Value
0 Resets to zero.
1 Resets to one.
Offset Module Base + 0x0000
0 1 2 3 4 5 6 7
R 0
MCPRE
0 0
DITH
0 MCTOIF
W w1c
Reset 0 0 0 0 0 0 0 0
Figure 35-2. Motor Controller Control Register 0 (MCCTL0)
Table 35-4. MCCTL0 field descriptions
Field Description
MCPRE Motor Controller Prescaler Select — MCPRE determines the prescaler value that sets the motor
controller timer counter clock frequency (f
TC
). The clock source for the prescaler is the peripheral bus
clock (f
BUS
) as shown in Figure 35-32. Writes to MCPRE will not affect the timer counter clock
frequency f
TC
until the start of the next PWM period.
00 f
TC
= f
Bus
01 f
TC
= f
Bus
/2
10 f
TC
= f
Bus
/4
11 f
TC
= f
Bus
/8
DITH Motor Control/Driver Dither Feature Enable (refer to Section 35.4.1.3.5, Dither Bit
(MCCTL0[DITH]))
0 Dither feature is disabled.
1 Dither feature is enabled.
MCTOIF Motor Controller Timer Counter Overflow Interrupt Flag — This bit is set when a motor controller
timer counter overflow occurs. The bit is cleared by writing a 1 to the bit.
0 A motor controller timer counter overflow has not occurred since the last reset or since the bit was
cleared.
1 A motor controller timer counter overflow has occurred.
Table 35-3. Register Access Conventions (continued)
Convention Description