Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
272 Freescale Semiconductor
The IPF is a 5-bit programmable up counter that is incremented by the selected clock source, according to
bits IF[0:3] in the EMIOSC[n] register.
Figure 9-38. lPF submodule diagram
The input signal is synchronized by the system clock. When a state change occurs in this signal, the 5-bit
counter starts counting up. As long as the new state is stable on the pin, the counter continues incrementing.
If a counter overflows occurs, the new pin value is validated. In this case, it is transmitted as a pulse edge
to the edge detector. If the opposite edge appears on the pin before validation (overflow), the counter is
reset. At the next pin transition, the counter starts counting again. Any pulse that is shorter than a full range
of the masked counter is regarded as a glitch and it is not passed on to the edge detector. A timing diagram
of the input filter is shown in Figure 9-39.
Figure 9-39. IPF example
The filter is not disabled during freeze state.
9.5.1.3 Clock Prescaler (CP)
The CP divides the GCP output signal to generate a clock enable for the internal counter of the Unified
Channels. The GCP output signal is prescaled by the value defined in Figure 9-17 according to the
UCPRE[0:1] bits in the EMIOSC[n] register. The prescaler is enabled by setting the UCPREN bit in
EMIOSC[n], and can be stopped at any time by clearing this bit, thereby stopping the internal counter in
the Unified Channel.
In order to ensure safe operation and avoid glitches, the following steps must be performed whenever any
update in the prescaling rate is desired:
1. Write 0 at both the GPREN bit in the EMIOSMCR register and the UCPREN bit in the EMIOSC[n]
register, thus disabling prescalers.
IF3
filter out
ipg_clk
Prescaled Clock
IF2 IF1 IF0
clk
FCK
EMIOSI
5-bit up counter
synchronizer
clock
Time
selected clock
EMIOSI
5-bit counter
filter out
IF
[0:3]
= 0010
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