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NXP Semiconductors MPC5606S - Page 253

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Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 251
EDPOL Edge Polarity bit
For input modes (except QDEC mode), the EDPOL bit asserts which edge triggers either the internal
counter or an input capture or a FLAG. When not shown in the mode of operation description, this bit
has no effect.
0 Trigger on a falling edge
1 Trigger on a rising edge
For QDEC (MODE[6] cleared), the EDPOL bit selects the count direction according to the direction
signal (UC[n] input).
0 Counts down when UC[n] is asserted
1 Counts up when UC[n] is asserted
Note: The UC[n1] EDPOL bit selects which edge clocks the internal counter of UC[n].
0 Trigger on a falling edge
1 Trigger on a rising edge
For QDEC (MODE[6] set), the EDPOL bit selects the count direction according to the phase
difference.
0 Internal counter decrements if phase_A is ahead of the phase_B signal
1 Internal counter increments if phase_A is ahead of the phase_B signal
Note: In order to operate properly, EDPOL bit must contain the same value in UC[n] and UC[n1].
For output modes, the EDPOL bit is used to select the logic level on the output pin.
0 A match on comparator A clears the output flip-flop, while a match on comparator B sets it
1 A match on comparator A sets the output flip-flop, while a match on comparator B clears it
MODE[0:6] Mode selection bits
The MODE[0:6] bits select the mode of operation of the Unified Channel, as shown in Table 9-20.
Note: If a reserved value is written to MODE, the results are unpredictable.
Table 9-16. UC ODISSL selection
ODISSL[0:1] eMIOS200_0 channel eMIOS200_1 channel Input signal
00 emios_flag_out[8] emios_flag_out[16] Output Disable Input 0
01 emios_flag_out[9] emios_flag_out[17] Output Disable Input 1
10 emios_flag_out[10] emios_flag_out[18] Output Disable Input 2
11 emios_flag_out[11] emios_flag_out[19] Output Disable Input 3
Table 9-17. UC internal prescaler clock divider
UCPRE[0:1] Divide ratio
00 1
01 2
10 3
11 4
Table 9-15. EMIOSC[n] field descriptions (continued)
Field Description

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