Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 361
12.3.4.7 Control Descriptor L0_7 Register
Figure 12-9 represents the Control Descriptor L0_7 Register.
Figure 12-9. Control Descriptor L0_7 Register
For the other 16 layers, the Control Descriptor Register set is identical.
12.3.4.8 Control Descriptor Cursor 1 Register (CtrlDescCursor_1)
Figure 12-10 represents the Control Descriptor Cursor 1 register.
Offset:
0x018 (CtrlDescL0_7)
0x034 (CtrlDescL1_7)
0x050 (CtrlDescL2_7)
0x06C (CtrlDescL3_7)
0x088 (CtrlDescL4_7)
0x094 (CtrlDescL5_7)
0x0C0 (CtrlDescL6_7)
0x0DC (CtrlDescL7_7)
0x0F8 (CtrlDescL8_7)
0x114 (CtrlDescL9_7
0x130 (CtrlDescL10_7)
0x14C (CtrlDescL11_7)
0x168 (CtrlDescL12_7)
0x184 (CtrlDescL13_7)
0x19C (CtrlDescL14_7)
0x1BC (CtrlDescL15_7) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0
TILE_VER_SIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0
TILE_HOR_SIZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-11. Control Descriptor L0_7 Register
Field Description
6–15
TILE_VER_SIZE
Height of the TILE (in pixels)
24–31
TILE_HOR_SIZE
Width of the TILE (in multiples of 16 pixels)
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