Stepper Motor Controller (SMC)
MPC5606S Microcontroller Reference Manual, Rev. 7
1150 Freescale Semiconductor
NOTE
Both equations are only valid if MCPER[PER] is not equal to 0. M = 1 for
left or right aligned mode, M = 2 for center aligned mode.
Table 35-22 shows examples of the SMC channel frequencies that can be generated based on different
peripheral bus clock frequencies and the prescaler value.
NOTE
Due to the selectable slew rate control of the outputs, clipping may occur on
short output pulses.
35.4.4 Output switching delay
In order to prevent large peak current draw from the motor power supply, selectable delays can be used to
stagger the high logic level to low logic level transitions on the SMC outputs. The timing delay, t
d
, is
determined by the MCCCx[CD] bits in the corresponding channel control register and is selectable
between 0, 1, 2, or 3 motor controller timer counter clock cycles.
NOTE
A PWM channel gets disabled at the next timer counter overflow without
notice of the switching delay.
35.4.5 Operation in SMC stop mode
All module clocks are stopped and the associated port pins are set to their inactive state, which is defined
by the state of the MCCTL1[RECIRC] bit. The SMC module registers stay the same as they were prior to
entering stop mode. Therefore, after exiting from stop mode, the associated port pins will resume to the
same functionality they had prior to entering stop mode.
35.4.6 Short-circuit detection
Each PWM pin is equipped with a short-circuit detection function. Hence, 24 instances (4 for each PWM
module) of the short-circuit detector exist.
Table 35-22. SMC Channel Frequencies (Hz),
MCPER[PER] = 256, MCCTL0[DITH] = 0, MCCCx[MCAM] = 0x2, 0x1
Prescaler
Peripheral Bus Clock Frequency
16 MHz 10 MHz 8 MHz 5 MHz 4 MHz
1 62500 39063 31250 19531 15625
1/2 31250 19531 15625 9766 7813
1/4 15625 9766 7813 4883 3906
1/8 7813 4883 3906 2441 1953
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