Error Correction Status Module (ECSM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 523
Chapter 16
Error Correction Status Module (ECSM)
16.1 Introduction
The Error Correction Status Module (ECSM) provides a myriad of miscellaneous control functions for the
device including program-visible information about configuration and revision levels, a reset status
register, wakeup control for exiting low-power modes, and optional features such as information on
memory errors reported by error-correcting codes.
The register protection module (see Appendix A, Registers Under Protection) provides access protection
for slave modules INTC, ECSM, MPU, STM, and SWT.
16.2 Overview
The Error Correction Status Module is mapped into the IPS space and supports a number of miscellaneous
control functions for the device.
16.3 Features
The ECSM includes these features:
• Program-visible information on the device configuration and revision
• Optional registers for capturing information on memory errors if error-correcting codes (ECC) are
implemented
• Optional registers to specify the generation of single- and double-bit memory data inversions for
test purposes if error-correcting codes are implemented
• XBAR_lite priority functions, including forcing round robin and high-priority enabling
• Spp_ips_reg_protection provides privileged-only access to selected on-platform slave devices:
INTC, ECSM, MPU, STM, and SWT
16.4 Memory map and register description
This section details the programming model for the Error Correction Status Module. This is a 128-byte
space mapped to the region serviced by an IPS bus controller.
16.4.1 Memory map
The Error Correction Status Module does not include any logic which provides access control. Rather, this
function is supported using the standard access control logic provided by the IPS controller.
Table 16-1 is a 32-bit view of the ECSM memory map.
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