NXP Semiconductors MPC5606S - Introduction

Peripheral Bridge (PBRIDGE)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 981
Chapter 28 
Peripheral Bridge (PBRIDGE)
28.1 Introduction
The PBRIDGE is the interface between the system bus and on-chip peripherals. It differs from that used
on Power Architecture products in the fact that it has a hard-wired configuration and cannot be configured
in software.
28.1.1 Overview
MPC5606S devices have one PBRIDGE, which provides an interface between the system bus and all
lower bandwidth peripherals. Accesses that fall within the address space of the PBRIDGE are decoded to
provide individual module selects for peripheral devices on the slave bus interface.
28.1.2 Features
The following list summarizes the key features of the PBRIDGE.
• Supports the slave interface signals. This interface is only meant for slave peripherals.
• Supports 32-bit slave peripherals. (Byte, halfword, and word reads and writes are supported to
each.)
28.1.3 Modes of operation
The PBRIDGE has only one operating mode.
28.2 Functional description
The PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus. It functions as
a protocol translator. Accesses that fall within the address space of the PBRIDGE are decoded to provide
individual module selects for peripheral devices on the slave bus interface.
28.2.1 Access support
Aligned 32-bit word accesses, halfword accesses, and byte accesses are supported for the peripherals.
Peripheral registers must not be misaligned, although no explicit checking is performed by the PBRIDGE.
NOTE
Data accesses that cross a 32-bit boundary are not supported.
28.2.1.1 Peripheral write buffering
Buffered writes are not supported by the MPC5606S PBRIDGE.