NXP Semiconductors MPC5606S - Appendix C; C.1 Changes between Revisions 6 and 7

Revision History
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1323
Appendix C 
Revision History
This appendix describes corrections to the MPC5606S Reference Manual. For convenience, the
corrections are grouped by revision.
C.1 Changes between revisions 6 and 7
Table C-1. Changes between revisions 6 and 7
Chapter Description
Throughout Updated document title to MPC5606S Microcontroller Reference Manual.
Editorial changes and improvements.
Analog-to-Digital
Converter (ADC)
In Tabl e 5-5 (ADC digital registers), added entry for channel 42 and removed entry for
channel 48. Added footnote explaining channel usage.
In Section 5.3.7, External decode signals delay, added this sentence to the end of the
paragraph: “When this programmed delay is taking place, the ADCSTATUS[0:2] field in
the Main Status Register (MSR) will display the value 010 (wait state).”
Added Note: at end of Section 5.3.1.5, Abort conversion: “NOTE: Setting either the ABORT
or ABORTCHAIN bit when no conversion is taking place can cause undetermined
operation of the next programmed conversion chain.”
Configurable
Enhanced Modular IO
Subsystem
(eMIOS200)
Removed REDC block from Figure 9-4 (eMIOS200 block diagram).
Removed bullet item “One Real-Time Signal Bus Client (REDC)” from Section 9.2.2,
Features.
Removed ETB and SRV bits from Figure 9-5 (eMIOS200 Module Configuration Register
(EMIOSMCR)).
Removed ETB and SRV bits from Ta bl e 9-9 (EMIOSMCR field descriptions).
Removed “(former STAC Bus)” legend 
from Figure 9-19 (Unified Channel block diagram).
Removed Section 9.5.3, Real-Time Signal Client submodule (REDC).
e200z0h Core Changed bullet in Section 14.2, Features from “Power saving modes: doze, nap, sleep and
wait” to “Dedicated power saving state: wait”.
Flash Memory In Tabl e 17-5 (Shadow block structure), removed “NVSRC” as a listed table and changed
its description to “Start of Shadow block.”
Added Warning at end of Section 17.2.5, User mode operation.
FlexCAN Removed Doze mode references: 
— In Figure 18-5 (Module Configuration Register (MCR)), changed bit 13 (DOZE)to
reserved. 
— Ta ble 18-8 (MCR field descriptions), changed bit 13 (DOZE) to reserved. 
— Section 18.4.9.1, Freeze mode. removed reference to Doze mode.
Inter-Integrated Circuit
Bus Controller Module
(I2C)
Removed Doze mode references: 
— Removed IBSDOZE bit in Figure 20-6 (I2C Bus Control Register (IBCR)). 
— Removed IBSDOZE bit in Table 20-8 (IBCR field descriptions).