NXP Semiconductors MPC5606S - Control Descriptor L0_5 Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
358 Freescale Semiconductor
12.3.4.5 Control Descriptor L0_5 Register
Figure 12-7 represents the control Descriptor L0_5 register. This register sets the maximum Chroma
Keying values for RGB.
Refer to Section 12.4.5.5, Alpha and Chroma-key blending, for a description of Chroma Keying.
12–15
BPP
Bits Per Pixel
0000 1 bpp
0001 2 bpp
0010 4 bpp
0011 8 bpp
0100 16 bpp (RGB565)
0101 24 bpp
0110 32 bpp (ARGB8888)
0111 Transparency mode 4 bpp
1000 Transparency mode 8bpp
1001 Luminance offset mode 4 bpp
1010 Luminance offset mode 8 bpp
1011 16 bpp (ARGB1555)
1100 16 bpp (ARGB4444)
1101–1111 Reserved
17–27
LUOFFS
Look Up Table offset. Value gives the offset to the start address of the CLUT or tile (when used
in internal tile mode) in the CLUT/TILE RAM.
29
BB
Chroma Keying
0OFF
1ON
30–31
AB
Alpha Blending
00 No Alpha blending
01 Blend only the pixels selected by chroma keying in case BB = 1
10 Blend the whole frame
11 Same functionality as 00 (No Alpha blending).
Table 12-8. CtrlDescL0_4 field descriptions (continued)
Field Description