NXP Semiconductors MPC5606S - Page 359

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 357
Figure 12-6. CtrlDescL0_4 Register
Offset:
0x00C (CtrlDescL0_4)
0x028 (CtrlDescL1_4)
0x044 (CtrlDescL2_4)
0x060 (CtrlDescL3_4)
0x07C (CtrlDescL4_4)
0x098 (CtrlDescL5_4)
0x0B4 (CtrlDescL6_4)
0x0D0 (CtrlDescL7_4)
0x0EC (CtrlDescL8_4)
0x108 (CtrlDescL9_4)
0x124 (CtrlDescL10_4)
0x140 (CtrlDescL11_4)
0x15C (CtrlDescL12_4)
0x178 (CtrlDescL13_4)
0x190 (CtrlDescL14_4)
0x1B0 (CtrlDescL15_4) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
EN
TILE
_EN
DAT
A_S
EL
SAF
ETY
_EN
TRANS BPP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0
LUOFFS
0
BB AB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-8. CtrlDescL0_4 field descriptions
Field Description
0
EN
Enable the layer
0OFF
1ON
1
TILE_EN
Enable the Tile mode
0OFF
1ON
2
DATA_SEL
Selects the Tile data either from MCU memory or CLUT
0 Tile mode data resides in the MCU memory
1 Tile mode data resides in the CLUT
3
SAFETY_EN
Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this
should be set to 0.
0 Safety mode is disabled
1 Safety mode is enabled for this layer
4–11
TRANS
Transparency Level. Specifies the alpha value for the layer. This value may be used by the
blending engine to blend pixels on this layer. Value can vary between 0-255 where 0 is
completely transparent and 255 is completely opaque.