NXP Semiconductors MPC5606S - Unimplemented Sprs and Read-Only Sprs

e200z0h Core
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 467
Figure 14-3. e200z0h User mode program model
14.3.1 Unimplemented SPRs and Read-only SPRs
e200z0h fully decodes the SPR field of the mfspr and mtspr instructions. If the SPR specified is undefined
and not privileged, an illegal instruction exception is generated. If the SPR specified is undefined and
privileged and the CPU is in user mode (MSR[PR=1]), a privileged instruction exception is generated. If
the SPR specified is undefined and privileged and the core is in supervisor mode (MSR[PR=0]), an illegal
instruction exception is generated.
For the mtspr instruction, if the SPR specified is read-only and not privileged, an illegal instruction
exception is generated. If the SPR specified is read-only and privileged and the core is in user mode
(MSR[PR=1]), a privileged instruction exception is generated. If the SPR specified is read-only and
privileged and the core is in supervisor mode (MSR[PR=0]), an illegal instruction exception is generated.
14.4 Instruction summary
e200z0h supports all VLE instructions described in the PowerPC™ VLE APU Definition version 1.2
together with the additional instructions for context save/restore.
USER Mode Program Model
SPR 515
Cache Configuration
L1CFG0
Cache Register (Read-only)
SPR 9
General-Purpose
Registers
Count Register
CTR
SPR 8
Link Register
LR
Condition Register
CR
GPR0
GPR1
GPR31
SPR 1
XER
XER
General Registers