NXP Semiconductors MPC5606S - Frequency Display Register (CMU_FDR)

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 229
8.10.5.2 Frequency Display Register (CMU_FDR)
8.10.5.3 High Frequency Reference Register FMPLL0 (CMU_HFREFR)
Address: Base + 0x04 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 FD[19:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FD[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-31. Frequency display register (CMU_FDR)
Table 8-30. Frequency Display Register (CMU_FDR) field descriptions
Field Description
12–31
FD
Measured frequency bits
This register displays the measured frequency FRC with respect to FOSC. The measured
value is given by the following formula: FRC = (FOSC × MD) / n, where n is the value in
the CMU_FDR register.
Offset: 0x08 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0
HFREF[11:0]
W
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Figure 8-32. High Frequency Reference Register FMPLL0
Table 8-31. High Frequency Reference Register FMPLL0 field descriptions
Field Description
20–31
HFREF
High Frequency reference value
These bits determine the high reference value for the FMPLL0 clock. The reference value
is given by: (HFREF[11:0]/16) × (FRC
fast
/4).