NXP Semiconductors MPC5606S - Unified Channel Memory Map

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 241
Whenever an access is performed to an absent register, an absent channel, or a reserved address, the
eMIOS200 responds asserting Transfer Error signal from the slave bus interface.
9.4.1.1 Unified Channel memory map
Addresses of Unified Channel registers are specified as offsets from the channel’s base address, otherwise
the eMIOS200 base address is used as reference.
Table 9-8 describes the Unified Channel memory map.
Table 9-7. eMIOS200 memory map
eMIOS200[n] Base Address Description Location
0x000
0x003
Module Configuration register (EMIOSMCR) on page 242
0x004
0x007
Global FLAG register (EMIOSGFLAG) on page 243
0x008
0x00B
Output Update Disable (EMIOSOUDIS) on page 244
0x00C
0x00F
Disable Channel (EMIOSUCDIS) on page 245
0x010
0x11F
Reserved —
0x120
0x21F
Channel [8]
to
Channel [15]
0x220
0x31F
Channel [16]
to
Channel [23]
0x320
0xFFF
Reserved —
Table 9-8. Unified Channel memory map
UC[n] base address Description
0x00
A register (EMIOSA[n])
0x04
B register (EMIOSB[n])
0x08
Counter register (EMIOSCNT[n])
0x0C Control register (EMIOSC[n])
0x10 Status register (EMIOSS[n])
0x14 Alternate A register (EMIOSALTA[n])
0x18–0x1F Reserved