NXP Semiconductors MPC5606S - Register Description

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
212 Freescale Semiconductor
The crystal oscillator clock can be further divided by a configurable factor in the range 1 to 32 to generate
the divided clock to match system requirements. This division factor is specified by the OSCDIV[4:0] bits
of the OSC_CTL register.
8.6.4 Register description
Note: OSC32, after it is enabled, is always on, but can be turned off in Standby mode by writing the OSCON bit.
Base Address: 0xC3FE_0040 Offset: 0x0000 Access: Supervisor: read/write, User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
OSC
BYP
0 0 0 0 0 0 0
EOCV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
M_
OSC
0 0 OSCDIV
I_
OSC
0 0 0 0 0
S_O
SC
OSC
ON
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-20. Crystal Oscillator Control Register (OSC_CTL)
Table 8-17. Crystal Oscillator Control Register (OSC_CTL) field descriptions
Field Description
0
OSCBYP
Crystal Oscillator bypass
This bit specifies whether the oscillator should be bypassed or not. Only software can set this bit.
System reset is needed to reset this bit.
0 Oscillator output is used as root clock.
1 EXTAL32 is used as root clock.
8–15
EOCV[7:0]:\
End of Count Value
These bits specify the end of count value to be used for comparison by the oscillator stabilization
counter OSCCNT after reset, or whenever it is switched on from the off state. This counting period
ensures that the external oscillator clock signal is stable before it can be selected by the system.
When the oscillator counter reaches the value of EOCV[7:0]
× 512, the oscillator available interrupt
request is generated. The reset value of this field depends on the device specification. The OSCCNT
counter will be kept under reset if oscillator bypass mode is selected.
16
M_OSC
Crystal oscillator clock interrupt mask
0 Crystal oscillator clock interrupt is masked.
1 Crystal oscillator clock interrupt is enabled.
19–23
OSCDIV[4:0]
Crystal oscillator clock division factor
These bits specify the crystal oscillator output clock division factor. The output clock is divided by the
factor OSCDIV
+ 1.
24
I_OSC
Crystal oscillator clock interrupt
This bit is set by hardware when the OSCCNT counter reaches the count value of EOCV[7:0] × 512.
It is cleared by writing a 1.
0 No oscillator clock interrupt occurred.
1 Oscillator clock interrupt pending.