NXP Semiconductors MPC5606S - Initialization;Application Information

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
512 Freescale Semiconductor
• Platform SRAM can be accessed with one wait-state when viewed from the AMBA-AHB data
phase
• All IPS reads require two wait-states, and IPS writes three wait-states, again viewed from the
system bus data phase
• Platform operates at 150 MHz
For an SRAM to IPS transfer:
PEAKreq = 150 MHz  [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec Eqn. 15-2
For an IPS to SRAM transfer:
PEAKreq = 150 MHz  [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec Eqn. 15-3
Assuming an even distribution of the two transfer types, the average Peak Request Rate would be:
PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec)  2 = 12.0 Mreq/sec Eqn. 15-4
The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a
cold start (where no channel is executing, DMA is idle) are:
• 11 cycles for a software (TCD.start bit) request
• 12 cycles for a hardware (ipd_req signal) request
Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from
the internal registering of the ipd_req signals. For the peak request rate calculations above, the arbitration
and request registering is absorbed in or overlap the previous executing channel.
NOTE
When channel linking or scatter/gather is enabled, a two cycle delay is
imposed on the next channel selection and startup. This allows the link
channel or the scatter/gather channel to be eligible and considered in the
arbitration pool for next channel selection.
15.5 Initialization/application information
15.5.1 DMA initialization
A typical initialization of the DMA is:
1. Write the DMACR register if a configuration other than the default is desired.
2. Write the channel priority levels into the DCHPRIn registers if a configuration other than the
default is desired.
3. Enable error interrupts in the DMAEEI registers if so desired.
4. Write the 32 byte TCD for each channel that may request service.
5. Enable any hardware service requests via the DMAERQ register.
6. Request channel service by either software (setting the TCD.start bit) or by hardware (slave device
asserting its ipd_req signal).