NXP Semiconductors MPC5606S - LCD Frontplane Enable Register 1 (FPENR1)

LCD Driver (LCD64F6B)
MPC5606S Microcontroller Reference Manual, Rev. 7
796 Freescale Semiconductor
22.4.2.5 LCD Frontplane Enable Register 1 (FPENR1)
Address: Base + 0x14 Access: User read/write
0 1 2 3 4 5 6 7
R
FP63EN FP62EN FP61EN FP60EN FP59EN FP58EN FP57EN FP56EN
W
Reset 0 0 0 0 0 0 0 0
8 9 10 11 12 13 14 15
R
FP55EN FP54EN FP53EN FP52EN FP51EN FP50EN FP49EN FP48EN
W
Reset 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23
R
FP47EN FP46EN FP45EN FP44EN FP43EN FP42EN FP41EN FP40EN
W
Reset 0 0 0 0 0 0 0 0
24 25 26 27 28 29 30 31
R
FP39EN FP38EN FP37EN FP36EN FP35EN FP34EN FP33EN FP32EN
W
Reset 0 0 0 0 0 0 0 0
Figure 22-6. LCD Frontplane Enable Register 1 (FPENR1)
Table 22-10. FPENR1 field descriptions
Field Description
0:31 FP[63:32]EN. Frontplane Output Enable.
The FP[63:32]EN bits enable the frontplane driver outputs. If LCDEN = 0, these bits have no effect on the
state of the I/O pins. It is recommended to set FP[63:32]EN bits before LCDEN is set.
0 Frontplane driver output disabled on FP[63:32].
1 Frontplane driver output enabled on FP[63:32].
Note: The implemented FP[n-1]EN bits depend on the number of implemented frontplanes.