Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 309
11.8.1.2 Slave mode
In Slave mode the DSPI responds to transfers initiated by an SPI master. The DSPI operates as bus slave
when the MSTR bit in the DSPIx_MCR is negated. The DSPI slave is selected by a bus master by having
the slave’s CS0_x asserted. In Slave mode the SCK is provided by the bus master. All transfer attributes
are controlled by the bus master, except the clock polarity, clock phase, and the number of bits to transfer,
which must be configured in the DSPI slave to communicate correctly.
11.8.1.3 Module Disable mode
The Module Disable mode is used for MCU power management. The clock to the non-memory-mapped
logic in the DSPI is stopped while in Module Disable mode. The DSPI enters the Module Disable mode
when the MDIS bit in DSPIx_MCR is set.
Refer to Section 11.8.8, Power-saving features, for more details on the Module Disable mode.
11.8.1.4 External Stop mode
For devices with low-power modes, the DSPI supports the Global Signal Stop mode mechanism. The DSPI
will not acknowledge the request to enter External Stop mode until it has reached a frame boundary. When
the DSPI has reached a frame boundary it will halt all operations and indicate that it is ready to have its
clocks shut off. The DSPI exits External Stop mode and resumes normal operation once the clocks are
turned on. Serial communications or register accesses made while in External Stop mode are ignored even
if the clocks have not been shut off yet. See Section 11.8.8, Power-saving features, for more details on the
External Stop mode.
11.8.1.5 Debug mode
The debug mode is used for system development and debugging. If the MCU is stopped by a debugger
while the DSPIx_MCR[FRZ] bit is set, the DSPI halts operation on the next frame boundary and enters a
stopped state. If the MCU is stopped by a debugger while the FRZ bit is cleared, the DSPI behavior is
unaffected and remains dictated by the module-specific mode and configuration of the DSPI. The FRZ bit
operation is only available when the CPU has an active debug mode.
See Figure 11-12 for a state diagram.
11.8.2 Start and stop of DSPI transfers
The DSPI has two operating states: Stopped and Running. The states are independent of DSPI
configuration. The default state of the DSPI is Stopped. In the Stopped state no serial transfers are initiated
in Master mode and no transfers are responded to in Slave mode. The Stopped state is also a safe state for
writing the various configuration registers of the DSPI without causing undetermined results. The TXRXS
bit in the DSPIx_SR is cleared in this state. In the Running state, serial transfers take place. The TXRXS
bit in the DSPIx_SR is set in the Running state.
Figure 11-12 shows a state diagram of the start and stop mechanism.
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