NXP Semiconductors MPC5606S - HSYN_PARA Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
368 Freescale Semiconductor
12.3.4.15 HSYN_PARA Register
Figure 12-17 represents the HSYN_PARA register. HSYN_PARA register sets timing parameters related
to the horizontal synchronization signal generation. The fields FP_H, BP_H, and PW_H stand for HSYNC
signal front-porch, back-porch, and active pulse width, respectively.
Figure 12-17. HSYN_PARA Register
12.3.4.16 VSYN_PARA Register
Figure 12-18 represents the VSYN_PARA register. VSYN_PARA register sets timing parameters related
to the vertical synchronization signal generation. The fields FP_V, BP_V, and PW_V stand for VSYNC
signal front-porch, back-porch, and active pulse width, respectively.
Table 12-18. DISP_SIZE field descriptions
Field Description
6–15
DELTA_Y
Sets the display size vertical resolution (in pixels)
24–31
DELTA_X
Sets the display size horizontal resolution (in multiples of 16 pixels)
Offset: 0x1DC Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
BP_H
0 0
PW_H[0:3]
W
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PW_H[4:8]
0 0
FP_H
W
Reset 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1
Table 12-19. HSYN_PARA field descriptions
Field Description
1–9
BP_H
HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
12–20
PW_H
HSYNC active pulse width (in pixel clock cycles).
23–31
FP_H
HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.