Voltage Regulators and Power Supplies
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1231
Two LVD_DIGs are provided in the design. One LVD_DIG is placed in the high power domain and senses
the HPREG/LPREG output, indicating that the 1.2 V output is stable. The other LVD_DIG is placed in the
standby domain and senses the standby 1.2 V supply level, indicating that the 1.2 V output is stable. The
reference voltage used for all LVDs is generated by the low-power reference generator and is trimmed for
LVD_DIG, using the bits LP[4:7]. Therefore, during the pre-trimming period, LVD_DIG exhibits higher
thresholds whereas, after trimming, the thresholds come within the desired range. Power-down pins are
provided for LVDs. When LVDs are powered down, their outputs are pulled high.
POR is required to initialize the chip during the voltage supply rise time. POR works only on the rising
edge of the main supply voltage. To ensure that it functions during the following rising edge of the supply
voltage, it is reset by the output of the ULVDM block when the main supply goes below the lower voltage
threshold of ULVDM.
POR is asserted on startup when the Vdd supply is above the minimum value of V
PORUP
(refer to the
MPC5606S Microcontroller Data Sheet for this value). It will be released only after the Vdd supply goes
above V
PORH
(refer to the MPC5606S Microcontroller Data Sheet for this value). Vdd above V
PORH
ensures that the power management module, including the internal LVD modules, are fully functional.
40.4.5 VREG digital interface
The voltage regulator digital interface provides the temporization delay at initial startup and at exit from
low-power modes. A signal indicating that the ultra low-power domain is powered is used at startup to
release reset to the temporization counter. At exit from low-power modes, the power-down for high power
regulator request signal is monitored by the digital interface and used to release reset to the temporization
counter. In both cases, on completion of the delay counter, an end-of-count signal is released; this is gated
with an other signal indicating that the main domain voltage is fine, in order to release the VREGOK
signal. This is used by MC_RGM to release the reset to the device. It manages other specific requirements,
including the transition between high power or low-power mode to ultra low-power mode, avoiding a
voltage drop below the permissible threshold limit of 1.08V.
The VREG digital interface also contains a control register to mask the 5 V LVD status from the voltage
regulator at startup.
To Next Page
Loading...
