Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 745
20.5.2.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such cases, it halts the bus clock and forces
the master clock into wait state until the slave releases the SCL line.
20.5.2.9 Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low, the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
20.5.3 Interrupts
20.5.3.1 General
The I
2
C module uses only one interrupt vector.
20.5.3.2 Interrupt Description
There are five types of internal interrupts in the I
2
C. The interrupt service routine can determine the
interrupt type by reading the Status Register.
I
2
C Interrupt can be generated on
• Arbitration Lost condition (IBAL bit set)
• Byte Transfer condition (TCF bit set)
• Address Detect condition (IAAS bit set)
• No Acknowledge from slave received when expected
• Bus Going Idle (IBB bit not set)
The I
2
C interrupt is enabled by the IBIE bit in the I
2
C Control Register. It must be cleared by writing 1 to
the IBIF bit in the interrupt service routine. The Bus Going Idle interrupt needs to be additionally enabled
by the BIIE bit in the IBIC register.
Table 20-11. Interrupt Summary
Interrupt Offset Vector Priority Source Description
I
2
C
Interrupt
— — — IBAL, TCF,
IAAS, IBB bits in
IBSR register
When any of IBAL, TCF or IAAS bits is set an interrupt may
be caused based on Arbitration lost, Transfer Complete or
Address Detect conditions. If enabled by BIIE, the
deassertion of IBB can also cause an interrupt, indicating
that the bus is idle.
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