NXP Semiconductors MPC5606S - Overload Frames

FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
706 Freescale Semiconductor
possible to select whether remote frames are accepted or not. For format C, remote frames are always
accepted (if they match the ID).
18.4.8.2 Overload frames
FlexCAN transmits overload frames due to detection of the following conditions on the CAN bus:
• Detection of a dominant bit in the first/second bit of Intermission
• Detection of a dominant bit at the 7th bit (last) of End-of-Frame field (Rx frames)
• Detection of a dominant bit at the 8th bit (last) of Error Frame delimiter or Overload Frame
delimiter
18.4.8.3 Time stamp
The value of the free-running timer is sampled at the beginning of the Identifier field on the CAN bus, and
is stored at the end of “move-in” in the TIME STAMP field, providing network behavior with respect to
time.
Note that the free-running timer can be reset upon a specific frame reception, enabling network time
synchronization. Refer to TSYN description in Section 18.3.4.2, Control Register (CTRL).
18.4.8.4 Protocol timing
Figure 18-16 shows the structure of the clock generation circuitry that feeds the CAN Protocol Interface
(CPI) submodule. The clock source bit (CLK_SRC) in the CTRL Register defines whether the internal
clock is connected to the output of a crystal oscillator (Oscillator Clock) or to the Peripheral Clock
(generally from a PLL). In order to guarantee reliable operation, the clock source should be selected while
the module is in Disable mode (bit MDIS set in the Module Configuration Register).
Figure 18-16. CAN engine clocking scheme
The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the
CAN bus timing. The crystal oscillator clock has better jitter performance than PLL generated clocks.
NOTE
This clock selection feature may not be available in all MCUs. A particular
MCU may not have a PLL, in which case it would have only the oscillator
clock, or it may use only the PLL clock feeding the FlexCAN module. In
these cases, the CLK_SRC bit in the CTRL Register has no effect on the
module operation.
Peripheral Clock (PLL)
Oscillator Clock (Xtal)
CLK_SRC
Prescaler
(1 .. 256)
Sclock
CPI Clock