Reset Generation Module (MC_RGM)
MPC5606S Microcontroller Reference Manual, Rev. 7
1092 Freescale Semiconductor
• An external reset event
• A ‘functional’ reset event configured via the RGM_FBRE register to assert the external reset
In this case, the external reset is asserted until the end of Phase3.
31.4.4 Functional Resets
A ‘functional’ reset indicates that an event has occurred after which it can be guaranteed that critical
register and memory content is still intact.
The status flag associated with a given ‘functional’ reset event (RGM_FES.F_<functional reset> bit) is
set when the ‘functional’ reset is asserted and the power-on reset is not asserted. It is possible for multiple
status bits to be set simultaneously, and it is software’s responsibility to determine which reset source is
the most critical for the application.
The ‘functional’ reset can be optionally disabled by software writing bit
RGM_FERD.D_<functional reset>.
NOTE
The RGM_FERD register can be written only once between two power-on
reset events.
An enabled functional reset will normally trigger a reset sequence starting from the beginning of Phase1.
Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence triggered by
a functional reset. When RGM_FESS.SS_<functional reset> is set, the associated ‘functional’ reset will
trigger a reset sequence starting directly from the beginning of Phase3, skipping Phase1 and Phase2. This
can be useful especially in case a functional reset should not reset the flash module.
31.4.5 Standby Entry Sequence
Standby mode can be entered only when the MC_RGM is in Idle. On Standby entry, the MC_RGM moves
to Phase1. The minimum duration counter in Phase1 does not start until Standby mode is exited. On entry
to Phase1 due to Standby mode entry, the resets for all power domains except power domain #0 are
asserted. During this time, RESET is not asserted as the external reset can act as a wakeup for the device.
There is an option to keep the flash inaccessible and in low-power mode on Standby exit by configuring
the DRUN mode before Standby entry so that the flash is in power-down or low-power mode. If the flash
is to be inaccessible, the Phase2 and Phase3 states do not wait for the flash to complete initialization before
exiting, and the reset to the flash remains asserted.
See the MC_ME chapter for details on the Standby and DRUN modes.
NOTE
If the device is in Standby mode and an external reset occurs, the MC_RGM
may not assert the external reset for the duration of the reset sequence even
when RGM_FBRE[BE_EXR]
= 0. This incorrect behavior occurs only if
the system releases the external reset before the end of reset sequence
Phase1.
To Next Page
Loading...
