NXP Semiconductors MPC5606S - Channel Interrupt Mask Register (CIMR[1..2])

Analog-to-Digital Converter (ADC)
MPC5606S Microcontroller Reference Manual, Rev. 7
150 Freescale Semiconductor
5.4.3.4 Channel Interrupt Mask Register (CIMR[1..2])
The 0 to 31 range shown below is the maximum range for the channel type. For the exact number of
available channels, please refer to Table 5-5.
CIMR1 = Enable bits for channels 32 to 63 (extended internal channels)
CIMR2 = Enable bits for channels 64 to 95 (external channels)
Table 5-11. IMR field descriptions
Field Description
0:24 Reserved
A write of any value has no effect. The read value is always 0.
25–26 Reserved
Must be kept at 0.
27 Reserved
Must be kept at 0.
28
MSKJEOC
Mask bit for JEOC
When set, the JEOC interrupt is enabled.
29
MSKJECH
Mask bit for JECH
When set, the JECH interrupt is enabled.
30
MSKEOC
Mask bit for EOC
When set, the EOC interrupt is enabled.
31
MSKECH
Mask bit for ECH
When set, the ECH interrupt is enabled.
Address: Base + 0x0028 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CIM
63
CIM
62
CIM
61
CIM
60
CIM
59
CIM
58
CIM
57
CIM
56
CIM
55
CIM
54
CIM
53
CIM
52
CIM
51
CIM
50
CIM
49
CIM
48
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CIM
47
CIM
46
CIM
43
CIM
44
CIM
43
CIM
42
CIM
41
CIM
40
CIM
39
CIM
38
CIM
37
CIM
36
CIM
35
CIM
34
CIM
33
CIM
32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-11. Channel Interrupt Mask Register 1 (CIMR1)