NXP Semiconductors MPC5606S - Power Domain Status Register (PCU_PSTAT)

Power Control Unit (MC_PCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 989
29.3.2.4 Power Domain Status Register (PCU_PSTAT)
This register reflects the power status of all available power domains.
29.4 Functional description
29.4.1 General
The MC_PCU controls all available power domains on a device mode basis. The PCU_PCONFn registers
specify during which system/user modes a power domain is powered up. The power state for each
individual power domain is reflected by the bits in the PCU_PSTAT register.
On a mode change, the MC_PCU evaluates which power domain(s) must change power state. The power
state is controlled by a state machine (FSM) for each individual power domain (see Figure
3-1) which
ensures a clean and safe state transition.
29.4.2 Reset / Power-On Reset
After any reset, the SoC will transition to the Reset mode during which all power domains are powered up
(see the MC_ME chapter). Once the reset sequence has been completed, the DRUN mode is entered and
software can begin the MC_PCU configuration.
29.4.3 MC_PCU Configuration
Per default, all power domains are powered in all modes other than Standby. Software can change the
configuration for each power domain on a mode basis by programming the PCU_PCONFn registers.
Address 0xC3FE_8040 Access: Supervisor read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PD2 PD1 PD0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Figure 29-5. Power Domain Status Register (PCU_PSTAT)
Table 29-4. Power Domain Status Register (PCU_PSTAT) field descriptions
Field Description
PDn Power status for power domain #n
0 Power domain is inoperable
1 Power domain is operable