FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
700 Freescale Semiconductor
Upon receiving the MB interrupt, the CPU should service the received frame using the following
procedure:
1. Read the Control and Status word (mandatory – activates an internal lock for this buffer).
2. Read the ID field (optional – needed only if a mask was used).
3. Read the Data field.
4. Read the Free Running Timer (optional – releases the internal lock).
Upon reading the Control and Status word, if the BUSY bit is set in the Code field, then the CPU should
defer the access to the MB until this bit is negated. Reading the Free Running Timer is not mandatory. If
not executed the MB remains locked, unless the CPU reads the Control and Status word of another MB.
Note that only a single MB is locked at a time. The only mandatory CPU read operation is the one on the
Control and Status word to assure data coherency (see Section 18.4.6, Data coherence).
The CPU should synchronize to frame reception by the status flag bit for the specific MB in one of the
interrupt flag registers (IFRL, IFRH) and not by the Code field of that MB. Polling the Code field does not
work because once a frame has been received and the CPU services the MB (by reading the Control and
Status word followed by unlocking the MB), the Code field will not return to EMPTY. It will remain
FULL, as explained in Table 18-5. If the CPU tries to work around this behavior by writing to the Control
and Status word to force an EMPTY code after reading the MB, the MB is actually deactivated from any
currently ongoing matching process. As a result, a newly received frame matching the ID of that MB may
be lost.
NOTE
Never do polling by reading directly the Control and Status word of the
MBs. Instead, read the interrupt flag registers (IFRL, IFRH).
Note that the received ID field is always stored in the matching MB; thus the contents of the ID field in an
MB may change if the match was due to masking. Note also that FlexCAN does receive frames transmitted
by itself if there exists an Rx matching MB, provided the SRX_DIS bit in the MCR is not asserted. If
SRX_DIS is asserted, FlexCAN will not store frames transmitted by itself in any MB, even if it contains
a matching MB, and no interrupt flag or interrupt signal will be generated due to the frame reception.
To be able to receive CAN frames through the FIFO, the CPU must enable and configure the FIFO during
Freeze mode (see
Section 18.4.7, Rx FIFO). Upon receiving the frames-available interrupt from FIFO, the
CPU should service the received frame using the following procedure:
1. Read the Control and Status word (optional – needed only if a mask was used for IDE and RTR
bits).
2. Read the ID field (optional – needed only if a mask was used).
3. Read the Data field.
4. Clear the frames available interrupt (mandatory – release the buffer and allow the CPU to read the
next FIFO entry).
18.4.5 Matching process
The matching process is an algorithm executed by the MBM that scans the MB memory looking for Rx
MBs programmed with the same ID as the one received from the CAN bus. If the FIFO is enabled, the
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