Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 633
• The volatile modify protection registers are read/write registers whose bits can be written at 0 or 1
by the user application.
A software mechanism is provided to independently lock/unlock each Low, Mid and High Address Space
Block against program and erase.
Software locking is done through the LML (Low/Mid Address Space Block Lock Register) or HBL (High
Address Space Block Lock Register) registers.
An alternate means to enable software locking for blocks of Low Address Space only is through the SLL
(Secondary Low/Mid Address Space Block Lock Register).
All these registers have a non-volatile image stored in Test flash (NVLML, NVHBL, NVSLL), so that the
locking information is kept on reset.
On delivery the Test flash non-volatile image is at all 1s, meaning all sectors are locked.
By programming the non-volatile locations in Test flash, the selected sectors can be unlocked.
Being the Test flash one time programmable (that is, not erasable), once unlocked the sectors cannot be
locked again.
Of course, on the contrary, all the volatile registers can be written at 0 or 1 at any time, therefore the user
application can lock and unlock sectors when desired.
17.3.9.2 Censored mode
The 80K flash memory macrocell does not contain a Shadow block and all the associated features to
manage the Censored mode. These must therefore be managed by the associated code flash memory
macrocell embedded in the same SoC.
17.4 Platform flash controller (PFLASH2P_LCA)
17.4.1 Introduction
This section provides an introduction to the 2-port Platform Flash Controller (PFLASH2P_LCA). The
PFLASH2P_LCA acts as the interface between two system bus master ports (AHB-Lite 2.v6) and up to
three banks of integrated low-cost 90-nm flash memory arrays. It intelligently converts the protocols
between the system bus ports and the dedicated flash array interfaces.
A block diagram of the e200z0h Power Architecture reduced product platform (RPP) reference design is
shown below in Figure 17-42 with the PFLASH2P_LCA module and its attached off-platform flash
memory arrays highlighted.
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