NXP Semiconductors MPC5606S - Control Descriptor L0_3 Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 355
Figure 12-4. CtrlDescL0_2 Register
12.3.4.3 Control Descriptor L0_3 Register
Figure 12-5 represents the control descriptor L0_3 register. This register sets the beginning address of
layer data.
Offset:
0x004 (CtrlDescL0_2)
0x020 (CtrlDescL1_2)
0x03C (CtrlDescL2_2)
0x058 (CtrlDescL3_2)
0x074 (CtrlDescL4_2)
0x090 (CtrlDescL5_2)
0x0AC (CtrlDescL6_2)
0x0C8 (CtrlDescL7_2)
0x0E4 (CtrlDescL8_2)
0x100 (CtrlDescL9_2)
0x11C (CtrlDescL10_2)
0x138 (CtrlDescL11_2)
0x154 (CtrlDescL12_2)
0x170 (CtrlDescL13_2)
0x18C (CtrlDescL14_2)
0x198 (CtrlDescL15_2) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0
POSY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0
POSX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-6. CtrlDescL0_2 field descriptions
Field Description
6–15
POSY
Amount of pixels from the top of display frame
20–31
POSX
Amount of pixels from the left of display frame