Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
664 Freescale Semiconductor
fetched will require wait states. The number of wait states is based on system clock frequency. However,
subsequent instructions contained in that 128-bit line buffer can be accessed without wait states.
Furthermore, with prefetching configured, the next sequential instructions outside the current line buffer
can be prefetched to different line buffer. After fetching all the instructions in current line buffer, the next
instruction is fetched for the next line buffer without delay.
Prefetching only helps performance when sequential accesses typically occur, such as for instructions.
Since data typically is not arranged sequentially (except for perhaps graphic data) prefetching for data
generally is not recommended.
The flash module on this device has two ports. Port 0 is always connected to the core. Port 1 is connected
to the other non-core masters (DCU and eDMA).
Configuring the flash bus interface parameters is done by writing to the Platform Flash Configuration
Registers PFCR0:1 and Platform Flash Access Protection Register PFAPR.
17.5.2 Flash memory setting recommendations
Table 17-70 provides an example of recommended settings for a common scenario with this device. This
example assumes Port 0 (core) instruction accesses are typically sequential, but not data. Port 1 (DCU and
eDMA) will not have any instruction accesses. For illustration, this example assumes port 1 accesses have
a significant amount of sequential data (such as for graphics) which are larger than a line buffer, so
prefetching data would make sense. If graphic data were not in the internal flash, then prefetching data on
port 1 would not be expected to be a benefit.
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