NXP Semiconductors MPC5606S - Baud Rate and Clock Delay Generation

Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
1036 Freescale Semiconductor
received SPI data that will be returned when QSPI_POPR is read. The POPNXTPTR field is incremented
every time the QSPI_POPR is read.
30.5.2.6.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time a SPI frame is transferred to
the RX FIFO the RX FIFO Counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the QSPI_SPISR is
asserted indicating an overflow condition. Depending on the state of the ROOE bit in the QSPI_MCR, the
data from the transfer that generated the overflow is either ignored or shifted into the shift register. If the
ROOE bit is asserted, the incoming data is shifted into the shift register. If the ROOE bit is negated, the
incoming data is ignored.
30.5.2.6.2 Draining the RX FIFO
Host software or other intelligent blocks can remove (pop) entries from the RX FIFO by reading the POP
RX FIFO Register (QSPI_POPR). A read of the QSPI_POPR decrements the RX FIFO Counter by one.
Attempts to pop data from an empty RX FIFO are ignored, the RX FIFO Counter remains unchanged. The
data returned from reading an empty RX FIFO is undetermined.
When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the QSPI_SPISR is set. The RFDF
bit is cleared when the RX FIFO is empty and the DMA controller indicates that a read from QSPI_POPR
is complete or by host software writing a 1 to the RFDF.
30.5.2.7 Baud Rate and Clock Delay Generation
The SCK frequency and the delay values for serial transfer are generated by dividing the system clock
frequency by a prescaler and a scaler with the option for doubling the baud rate. Figure 30-25 shows
conceptually how the SCK signal is generated.
Figure 30-25. Communications Clock Prescalers and Scalers
30.5.2.7.1 Baud Rate Generator
The Baud Rate is the frequency of the Serial Communication Clock (SCK). The system clock is divided
by a prescaler (PBR) and scaler (BR) to produce SCK with the possibility of halving the scaler division.
The DBR, PBR and BR fields in the QSPI_CTAR registers select the frequency of SCK by the formula in
the BR[0:3] field description. Table 30-38 shows an example of how to compute the baud rate.
SCK
System Clock
Prescaler
1
Scaler
1+DBR