Interrupt Controller (INTC)
MPC5606S Microcontroller Reference Manual, Rev. 7
756 Freescale Semiconductor
 
cross a register boundary. These supported accesses include types and sizes of eight bits, aligned 16 bits, 
misaligned 16 bits to the middle two bytes, and aligned 32 bits.
Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or 
32-bit access, provided that the access does not cross a 32-bit boundary.
In software vector mode, the side effects of a read of INTC_IACKR are the same regardless of the size of 
the read. In either software or hardware vector mode, the size of a write to either 
INTC_SSCIR0_3–INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of the write.
21.5.2.1 INTC Module Configuration Register (INTC_MCR)
The module configuration register is used to configure options of the INTC.
21.5.2.2 INTC Current Priority Register for Processor (INTC_CPR)
Offset: 0x0000  Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 0 0 0 0 VTES 0 0 0 0 HVEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-2. INTC Module Configuration Register (INTC_MCR)
Table 21-3. INTC_MCR field descriptions 
Field Description
26
VTES
Vector table entry size. Controls the number of 0s to the right of INTVEC in Section 21.5.2.3, INTC 
Interrupt Acknowledge Register (INTC_IACKR)). If the contents of INTC_IACKR are used as an 
address of an entry in a vector table as in software vector mode, then the number of rightmost 0s 
will determine the size of each vector table entry. VTES impacts software vector mode operation but 
also affects INTC_IACKR[INTVEC] position in both hardware vector mode and software vector 
mode.
0 4 bytes.
1 8 bytes.
31
HVEN
Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector 
mode. Refer to 
Section 21.4, Modes of operation, for the details of the handshaking with the 
processor in each mode.
0 Software vector mode.
1 Hardware vector mode.