Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
328 Freescale Semiconductor
11.8.8.2 Module Disable mode
Module Disable mode is a module-specific mode that the DSPI can enter to save power. Host software can
initiate the Module Disable mode by writing a 1 to the MDIS bit in the DSPIx_MCR. In Module Disable
mode, the DSPI is in a dormant state, but the memory-mapped registers are still accessible. Certain read
or write operations have a different effect when the DSPI is in Module Disable mode. Reading the RX
FIFO pop register does not change the state of the RX FIFO. Likewise, writing to the TX FIFO push
register does not change the state of the TX FIFO. Clearing either of the FIFOs does not have any effect
in Module Disable mode. Changes to the DIS_TXF and DIS_RXF fields of the DSPIx_MCR do not have
any effect in Module Disable mode. In Module Disable mode, all status bits and register flags in the DSPI
return the correct values when read, but writing to them has no effect. Writing to the DSPIx_TCR during
Module Disable mode does not have an effect. Interrupt and DMA request signals cannot be cleared while
in the Module Disable mode.
11.8.8.3 Slave interface signal gating
The DSPI module enable signal is used to gate slave interface signals such as address, byte enable,
read/write, and data. This prevents toggling slave interface signals from consuming power unless the DSPI
is accessed.
11.9 Initialization and application information
11.9.1 How to change queues
DSPI queues are not part of the DSPI module, but the DSPI includes features in support of queue
management. Queues are primarily supported in SPI configuration. This section presents an example of
how to change queues for the DSPI.
1. The last command word from a queue is executed. The EOQ bit in the command word is set to
indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag (EOQF) in the DSPIx_SR is set.
3. The setting of the EOQF flag disables both serial transmission and serial reception of data, putting
the DSPI in the Stopped state. The TXRXS bit is negated to indicate the Stopped state.
4. The eDMA continues to fill the TX FIFO until it is full or until step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned
to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable request bits in
the eDMA controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading the
RXCNT in DSPIx_SR or by checking RFDF in the DSPIx_SR after each read operation of the
DSPIx_POPR.
7. Modify DMA descriptor of TX and RX channels for new queues.
8. Flush TX FIFO by writing a 1 to the CLR_TXF bit in the DSPIx_MCR register and flush the RX
FIFO by writing a 1 to the CLR_RXF bit in the DSPIx_MCR register.
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