NXP Semiconductors MPC5606S - Parameter Error Status (PARR_ERR) Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
384 Freescale Semiconductor
12.3.4.28 Parameter Error Status (PARR_ERR) register
Figure 12-37 shows the parameter error status register.
An error in a layer can occur under the following conditions:
a) Number of pixels in a tile > maximum tile memory size in case of Tile bandwidth optimized
mode (when in internal memory mode)
b) There is an automatic error checking mechanism when a layer is enabled that detects a
non-valid horizontal size and color format combination. See
Section 12.4.5.3, Layer size and
positioning, for details.
These errors are grouped into a single bit error for each layer. The parameter error specific to each layer is
signaled only when the layer is enabled.
Table 12-31. PDI Status Mask Register field descriptions
Field Description
22
m_pdi_blanking_er
r
pdi_blanking_err interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
23
m_pdi_ecc_err2
pdi_ecc_err2 interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
24
m_pdi_ecc_err1
pdi_ecc_err1 interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
25
m_pdi_lock_lost
pdi_lock_lost interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
26
m_pdi_lock_det
pdi_lock_det interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
27
m_pdi_vsync_det
pdi_vsync_det interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
28
m_pdi_hsync_det
pdi_hsync_det interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
29
m_pdi_de_det
pdi_de_det interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
30
m_pdi_clk_lost
pdi_clk_lost interrupt mask
0 Interrupt is not masked
1 Interrupt is masked
31
m_pdi_clk_det
pdi_clk_det interrupt mask
0 Interrupt is not masked
1 Interrupt is masked