IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5606S Microcontroller Reference Manual, Rev. 7
718 Freescale Semiconductor
19.6 External signal description
The JTAGC consists of four signals that connect to off-chip development tools and allow access to test
support functions. The JTAGC signals are outlined in Table 19-1.
All four JTAG pins (TCK/TMS/TDI/TDO) are shared with GPIO pins, so that the software may configure
these pins as input/output by programming the appropriate registers.
To ensure the proper working of JTAG, these registers have a reset value such that these pins behave as
JTAG pins when the POR is lifted:
• TDI: input/pullup
• TCK: input/pullup
• TMS: input/pullup
• TDO: high-impedance/pull disabled
On entry to Standby mode the TDO pin goes to the high-Z/pull-disabled state. Some external debugger
connections may expect the TDO to be in a known state during standby, so an external pullup or pulldown
may be required for correct operation when debugging Standby.
NOTE
The JTAG Clock (TCK) typically operates at a frequency well below the
system clock frequency, as specified in the MPC5606S Microcontroller
Data Sheet. In some cases, however, the system clock frequency may be
lowered significantly from the normal operating range. If the system clock
frequency is reduced below the frequency of TCK, it will no longer be
possible to communicate with the Nexus Port Controller Port Configuration
Register (NPC_PCR).
19.7 Memory map and register description
This section provides a detailed description of the JTAGC registers accessible through the TAP interface,
including data registers and the instruction register. Individual bit-level descriptions and reset states of
each register are included. These registers are not memory-mapped and can only be accessed through the
TAP.
Table 19-1. JTAG signal properties
Name I/O Function Reset State
TCK I Test clock Pullup
TDI I Test data in Pullup
TDO O Test data out High Z
TMS I Test mode select Pullup
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