Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
240 Freescale Semiconductor
These modes are described in Section 9.5.1.1, UC modes of operation.
Each channel can have a specific set of modes implemented, according to device requirements.
If an unimplemented mode is selected, the results are unpredictable, such as writing a reserved value to
MODE[0:6] in
Section 9.4.2.8, eMIOS200 UC Control Register (EMIOSC[n]).
9.3 External signal description
9.3.1 Overview
Each channel has one external input and one external output signal, as described in Table 9-6. Depending
on the chip integration, the input and output signals can be connected to two separate pins, or to a single
bidirectional pin.
9.3.2 Detailed signal descriptions
9.3.2.1 emiosi[n] — eMIOS200 Channel Input Signal
emiosi[n] is synchronized and filtered by the input programmable filter (IPF). The output of the IPF is then
used by the channel logic and is available to be read by the MCU through the UCIN bit of the EMIOSS[n]
register.
9.3.2.2 emioso[n] — eMIOS200 Channel Output Signal
emioso[n] is a registered output and is available for reading by the MCU through the UCOUT bit of the
EMIOSS[n] register. Whilst the channel is operating in input modes the signal state is unknown.
9.3.2.3 emios_flag_out[n] — eMIOS200 Channel Flag Signal
emios_flag_out[n] outputs the state of F[n] bit of the EMIOSGFLAG register.
9.4 Memory map and register description
9.4.1 Memory map
The overall address map organization is shown in Table 9-7.
Table 9-6. External signals
Signal Direction Function Reset State Pullup
emiosi[n] Input eMIOS200 Channel n input — Chip-dependent
emioso[n] Output eMIOS200 Channel n output 0/ Hi-Z
1
1
Value “0” refers to the reset value of the signal. Hi-Z refers to the state of the external pin if a tristate output buffer
is controlled by the corresponding ipp_obe_emios_ch[n] signal.
Chip-dependent
emios_flag_out[n] Output eMIOS200 Channel n flag 0 Chip-dependent
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