NXP Semiconductors MPC5606S - Memory Map and Register Definition

LCD Driver (LCD64F6B)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 789
22.4 Memory map and register definition
22.4.1 Memory map
Table 22-5. Block memory map
Offset or
Address
Register Access Reset Value Location
General Registers
0x00 LCD Control Register (LCDCR) R/W 0x0000_0000 on page 790
0x04 LCD Prescaler Control Register (LCDPCR) R/W 0x0000_0000 on page 793
0x08 LCD Contrast Control Register (LCDCCR) R/W 0x0000_0000 on page 794
0x0C Reserved
0x10 LCD Frontplane Enable Register 0 (FPENR0) R/W 0x0000_0000 on page 795
0x14 LCD Frontplane Enable Register 1 (FPENR1) R/W 0x0000_0000 on page 796
0x18 Reserved
0x1C Reserved
0x20 LCDRAM (Location 0) R/W 0x0000_0000 on page 797
0x24 LCDRAM (Location 1) R/W 0x0000_0000 on page 798
0x28 LCDRAM (Location 2) R/W 0x0000_0000 on page 799
0x2C LCDRAM (Location 3) R/W 0x0000_0000 on page 800
0x30 LCDRAM (Location 4) R/W 0x0000_0000 on page 801
0x34 LCDRAM (Location 5) R/W 0x0000_0000 on page 802
0x38 LCDRAM (Location 6) R/W 0x0000_0000 on page 803
0x3C LCDRAM (Location 7) R/W 0x0000_0000 on page 804
0x40 LCDRAM (Location 8)
1
1
End of implemented RAM for 36 FPs
R/W 0x0000_0000 on page 805
0x44 LCDRAM (Location 9)
2
2
End of implemented RAM for 40 FPs
R/W 0x0000_0000 on page 806
0x48 LCDRAM (Location 10)
3
3
End of implemented RAM for 44 FPs
R/W 0x0000_0000 on page 807
0x4C LCDRAM (Location 11)
4
4
End of implemented RAM for 48 FPs
R/W 0x0000_0000 on page 808
0x50 LCDRAM (Location 12)
5
5
End of implemented RAM for 52 FPs
R/W 0x0000_0000 on page 809
0x54 LCDRAM (Location 13)
6
R/W 0x0000_0000 on page 810
0x58 LCDRAM (Location 14)
7
R/W 0x0000_0000 on page 811
0x5C LCDRAM (Location 15)
8
R/W 0x0000_0000 on page 812