Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 55
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
1.5.6 Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems.
For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral
to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC
provides a unique vector for each interrupt request source for quick determination of which ISR needs to
be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the
execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request,
the priority of each interrupt request is software-configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority can be raised temporarily so that all tasks which share the resource cannot preempt each other.
Multiple processors can assert interrupt requests to each other through software-settable interrupt requests.
These same software-settable interrupt requests also can be used to break the work involved in servicing
an interrupt request into a high-priority portion and a low-priority portion. The high-priority portion is
initiated by a peripheral interrupt request, but then the ISR asserts a software-settable interrupt request to
finish the servicing in a lower priority ISR. Therefore these software-settable interrupt requests can be used
instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following
features:
• Unique 9-bit vector for each of the possible 128 separate interrupt sources
• Eight software triggerable interrupt sources
• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
• Ability to modify the ISR or task priority
— Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing
shared resources
• External NMI directly accessing the main core critical interrupt mechanism
• 32 external interrupts
1.5.7 QuadSPI serial flash controller
The QuadSPI module enables use of external serial flash memories supporting single, dual, and quad
modes of operation. It features the following:
• Memory mapping of external serial flash memory
• Automatic serial flash read command generation by CPU, DMA, or DCU read access on AHB bus
• Supports single, dual, and quad serial flash read commands
• Flexible buffering scheme to maximize read bandwidth of serial flash
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