NXP Semiconductors MPC5606S - MPC5606 S Family Comparison

Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 43
• Clock Generation Module (MC_CGM)
— Generates system clock sources
— Provides a unified register interface, enabling access to all clock sources.
• Clock Monitor Unit (CMU)
— Monitors the integrity of the main crystal oscillator and the PLL
— Acts as a frequency meter, measuring the frequency of one clock source vs. a reference clock
• Mode Entry Module (MC_ME) controls the System-on-Chip (SoC) mode, that is, Run, Halt, Stop,
or Standby, and mode transition sequences. Also manages power control, voltage regulator, clock
generation and clock management modules.
• Power Control Unit (MC_PCU) implements Standby mode entry/exit and controls connections to
power domains
• Reset Generation Module (MC_RGM) manages reset assertion and release to the device at initial
startup
• Sound generation module supports monophonic and polyphonic sound
• LCD controller module
• Six gauge drivers with Stepper Stall Detect (SSD)
• Display Control Unit (DCU) designed to interface with TFT LCD displays. Generates all signals
required to drive the display and offers blending of four-plane data of up to 16 layers. Also has the
capability of displaying real time digital video in the background plane.
• Second generation Direct Memory Access (DMA2) controller provides fast data transfer with
minimal intervention from host processor
• On-chip voltage regulator controller for regulating 5 V down to 1.2 V for core logic
• JTAG (IEEE 1149.1) Nexus port for application development with optional Nexus 2+ trace port.
• The MPC5606S microcontroller is offered in the following packages:
— 144-pin LQFP, 0.5mm pitch, 20 mm × 20 mm outline
— 176-pin LQFP, 0.5mm pitch, 24 mm × 24 mm outline
— 208-ball MAPBGA, 1 mm ball pitch, 17 mm × 17 mm outline (development purposes only;
not a volume production package)
1.2 MPC5606S family comparison
Table 1-1 and Table 1-2 report the memory scaling of code flash memory and RAM.
Table 1-1. Code flash memory scaling
Memory Size Start Address End Address
256 KB 0x00000000 0x0003FFFF
512 KB 0x00000000 0x0007FFFF
1 MB 0x00000000 0x000FFFFF