NXP Semiconductors MPC5606S - Page 44

Overview
MPC5606S Microcontroller Reference Manual, Rev. 7
42 Freescale Semiconductor
• 160 KB on-chip non-ECC graphics SRAM with RAM controller
• A Memory Protection Unit (MPU) provides basic memory access permission and ensures
separation between different codes and data.
• A Boot Assist Module (BAM) with 8 KB dedicated ROM for embedded boot code
• Two frequency-modulated phase-locked loop (FMPLL) modules
• Interrupt controller (INTC) with 126 peripheral interrupt sources and eight software interrupts
• A 10-bit analog-to-digital converter (ADC) with a minimum conversion time of 1 µs
— 16 internal channels
— Up to 8 external channels
• Two enhanced Modular Input Output System (eMIOS) provide ability to generate or measure time
events
— One 8-channel, one 16-channel
— 16-bit counter width
— Configurable—can implement:
– Up to 24 IC/OC channels
– Up to 16 pulse width modulation (PWM) channels
– Up to 5 modulus counters
• Two serial communication interface (LINFlex) modules:
— LINFlex 0 and 1 are master-capable
— LINFlex 0 is also slave-capable
• Two DSPI (Deserial Serial Peripheral Interface) modules for communications with external
devices
• QuadSPI module
• Four Inter-integrated circuit (I
2
C) internal bus controllers with master/slave bus interface
• Up to two enhanced full CAN (FlexCAN) modules with 64 configurable message buffers
• System timers:
— One System Timer Module (STM)—included in processor platform
— Four Periodic Interrupt Timer (PIT) timers (including ADC trigger)
— One Real Time Counter (RTC) timer for timekeeping applications.
• Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus
masters
• System Integration Unit Lite (SIUL) manages resets, external interrupts, GPIO, and pad control
— 14 external interrupts
— Supports up to 133 GPIO pads
— 32-bit data bus width
• System Status and Configuration Module (SSCM)
— Provides information for identification of the device, last boot mode, or debug status
— Provides an entry point for censorship password mechanism