Analog-to-Digital Converter (ADC)
MPC5606S Microcontroller Reference Manual, Rev. 7
160 Freescale Semiconductor
5.4.8 Delay registers
5.4.8.1 Decode Signals Delay Register (DSDR)
Reset value: 0x0000_0000
5.4.8.2 Power-down Exit Delay Register (PDEDR)
Reset value: 0x0000_0000
Address:
Base + 0x00C4 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 DSD[0:7]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-24. Decode Signals Delay Register (DSDR)
Table 5-22. Decode Signals Delay Register (DSDR) field descriptions
Field Description
0–23 Reserved
A write of any value has no effect. The read value is always 0.
24–31
DSD[0:7]
Delay between the external decode signals and the start of the sampling phase
It is used to take into account the settling time of the external multiplexer.
The decode signal delay is calculated as: DSD × 1/frequency of system clock. For the case when ADC
clock = Peripheral Clock/2, the DSD bit field has to be incremented by 2 to see an additional ADC clock
cycle delay on the decode signal. For example:
0000 0 ADC clock cycle delay.
0010 1 ADC clock cycle delay.
0100 2 ADC clock cycle delay.
0110 3 ADC clock cycle delay.
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