Analog-to-Digital Converter (ADC)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 161
Address:
Base + 0x00C8 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0
PDED[0:7]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-25. Power-down Exit Delay Register (PDEDR)
Table 5-23. Power-down Exit Delay Register (PDEDR) field descriptions
Field Description
0–23 Reserved
A write of any value has no effect. The read value is always 0.
24–31
PDED[0:7
]
Delay between the power-down bit reset and the start of conversion
The power down delay is calculated as: PDED × 1/frequency of ADC clock.
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