Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 287
• Programmable transfer attributes on a per-frame basis
— 8 clock and transfer attribute registers
— Serial clock with programmable polarity and phase
— Programmable delays
– CS to SCK delay
– SCK to CS delay
– Delay between frames
— Programmable serial frame size of 4 to 16 bits, expandable with software control
— Continuously held chip select capability
• 3 peripheral chip selects, expandable to 64 with external demultiplexer
• Deglitching support for up to 32 peripheral chip selects with external demultiplexer
• 2 DMA conditions for SPI queues residing in RAM or flash
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
• 6 interrupt conditions:
– End of queue reached (EOQF)
– TX FIFO is not full (TFFF)
– Transfer of current frame complete (TCF)
– RX FIFO is not empty (RFDF)
– FIFO overrun (attempt to transmit with an empty TX FIFO or serial frame received while
RX FIFO is full) (RFOF)
– FIFO under flow (slave only and SPI mode, the slave is asked to transfer data when the TX
FIFO is empty) (TFUF)
• Modified SPI transfer formats for communication with slower peripheral devices
• Continuous serial communications clock (SCK)
11.5 Modes of operation
The DSPI has five modes of operation. These modes can be divided into two categories:
• Module-specific modes such as master, slave, and Module Disable modes
• MCU-specific modes such as external stop and debug modes
The module-specific modes are entered by host software writing to a register. The MCU-specific modes
are controlled by signals external to the DSPI. The MCU-specific modes are modes that the entire device
may enter, in parallel to the DSPI being in one of its module-specific modes.
11.5.1 Master mode
Master mode allows the DSPI to initiate and control serial communication. In this mode, the SCK and CSn
signals are controlled by the DSPI and configured as outputs. (SOUT is always an output.)
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