NXP Semiconductors MPC5606S - SYN_POL Register

Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 369
Figure 12-18. VSYN_PARA Register
12.3.4.17 SYN_POL Register
Figure 12-19 represents the SYN_POL register. SYN_POL register selects polarity for corresponding
synchronize signals (HSYNC, VSYNC, CSYNC), and controls the bypass of HSYNC or VSYNC with
CSYNC signal.
Figure 12-19. SYN_POL Register
Offset: 0x1E0 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0
BP_V
0 0
PW_V[0:3]
W
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PW_V[4:8]
0 0
FP_V
W
Reset 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1
Table 12-20. VSYN_PARA field descriptions
Field Description
1–9
BP_V
VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1.
12–20
PW_V
VSYNC active pulse width (in horizontal line cycles).
23–31
FP_V
VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1.
Offset: 0x1E4 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0
INV_PDI_DE INV_PDI_HS
INV_PDI_VS
INV_PDI_CLK
INV_PXCK
NEG
BP_VS
BP_HS
INV_CS
INV_VS
INV_HS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0