NXP Semiconductors MPC5606S - Register Map

Register Map
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1289
Threshold Register 0 THRHLR0 32-bit Base + 0x060
Threshold Register 1 THRHLR1 32-bit Base + 0x064
Threshold Register 2 THRHLR2 32-bit Base + 0x068
Threshold Register 3 THRHLR3 32-bit Base + 0x06C
Reserved — — Base +
(0x070–0x094)
Conversion Timing Register 1 CTR1 32-bit Base + 0x098
Conversion Timing Register 2 CTR2 32-bit Base + 0x09C
Reserved — — Base +
(0x0A0–0x0A4)
Normal Conversion Mask Register 1 NCMR1 32-bit Base + 0x0A8
Normal Conversion Mask Register 2 NCMR2 32-bit Base + 0x0AC
Reserved — — Base +
(0x0B0–0x0B4)
Injected Conversion Mask Register 1 JCMR1 32-bit Base + 0x0B8
Injected Conversion Mask Register 2 JCMR2 32-bit Base + 0x0BC
Reserved — — Base + 0x0C0
Decode Signals Delay Register DSDR 32-bit Base + 0x0C4
Power-down Exit Delay Register PDEDR 32-bit Base + 0x0C8
Reserved — — Base +
(0x0CC–0x17C)
Channel 32 Data Register CDR32 32-bit Base + 0x180
Channel 33 Data Register CDR33 32-bit Base + 0x184
Channel 34 Data Register CDR34 32-bit Base + 0x188
Channel 35 Data Register CDR35 32-bit Base + 0x18C
Channel 36 Data Register CDR36 32-bit Base + 0x190
Channel 37 Data Register CDR37 32-bit Base + 0x194
Channel 38 Data Register CDR38 32-bit Base + 0x198
Channel 39 Data Register CDR39 32-bit Base + 0x19C
Channel 40 Data Register CDR40 32-bit Base + 0x1A0
Channel 41 Data Register CDR41 32-bit Base + 0x1A4
Channel 43 Data Register CDR43 32-bit Base + 0x1AC
Channel 44 Data Register CDR44 32-bit Base + 0x1B0
Channel 45 Data RegisteR CDR45 32-bit Base + 0x1B4
Table B-2. Detailed register map (continued)
Register description Register Name
Used
Size
Address