NXP Semiconductors MPC5606S - Chapter 33 Reset Effects on SRAM Accesses

Static RAM (SRAM)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 1107
• Previous operation: Lists the valid types of SRAM operations that can precede the current SRAM
operation (valid operation during the preceding clock)
• Wait states: Lists the number of wait states (bus clocks) the operation requires which depends on
the combination of the current and previous operation
33.6.2 Reset effects on SRAM accesses
Asynchronous reset will possibly corrupt RAM if it asserts during a read or write operation to SRAM. The
completion of that access depends on the cycle at which the reset occurs. Data read from or written to
SRAM before the reset event occurred is retained, and no other address locations are accessed or changed.
In case of no access ongoing when reset occurs, the RAM corruption does not happen.
Instead synchronous reset (SW reset) should be used in controlled function (without RAM accesses) in
case initialization procedure is needed without RAM initialization.
33.7 Functional description
ECC checks are performed during the read portion of an SRAM ECC read/write (R/W) operation, and
ECC calculations are performed during the write portion of a read/write (R/W) operation. Because the
ECC bits can contain random data after the device is powered on, the SRAM must be initialized by
Table 33-3. Number of wait states required for SRAM operations
Current Operation Previous Operation Number of Wait States Required
Read Operation
Read Idle
1
Pipelined read
8-, 16-, or 32-bit write
0
(read from the same address)
1
(read from a different address)
Pipelined read Read 0
Write Operation
8-, or 16-bit write Idle
1
Read
Pipelined 8-, or 16-bit write
2
32-bit write
8-, or 16-bit write 0
(write to the same address)
Pipelined 8-, 16-, or 32-bit
write
8-, 16-, or 32-bit write 0
32-bit write Idle
032-bit write
Read