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NXP Semiconductors MPC5606S - Rx Individual Mask Registers (RXIMR0-RXIMR63)

NXP Semiconductors MPC5606S
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FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
696 Freescale Semiconductor
18.3.4.13 Rx Individual Mask Registers (RXIMR0RXIMR63)
These registers are used as acceptance masks for ID filtering in Rx MBs and the FIFO. If the FIFO is not
enabled, one mask register is provided for each available Message Buffer, providing ID masking capability
on a per Message Buffer basis. When the FIFO is enabled (FEN bit in MCR is set), the first eight Mask
Registers apply to the eight elements of the FIFO filter table (on a one-to-one correspondence), while the
rest of the registers apply to the regular MBs, starting from MB8.
The Individual Rx Mask Registers are implemented in RAM, so they are not affected by reset and must be
explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the
module is in Freeze mode. Out of Freeze mode, write accesses are blocked and read accesses will return
all zeroes. Furthermore, if the BCC bit in the MCR Register is negated, any read or write operation to these
registers results in an access error.
Address: See Tabl e 18-19 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-15. Rx Individual Mask Registers (RXIMR0–RXIMR63)
Table 18-18. Rx Individual Mask Registers (RXIMR0–RXIMR63) field descriptions
Field Description
0-31
MI31–MI0
Mask Bits
For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the
mask bits affect all bits programmed in the filter table (ID, IDE, RTR).
0 The corresponding bit in the filter is a don’t-care bit
1 The corresponding bit in the filter is checked against the one received
Table 18-19. RXIMR0–RXIMR31 addresses
Address Register Address Register
Base + 0x0880 RXIMR0 Base + 0x08C0 RXIMR16
Base + 0x0884 RXIMR1 Base + 0x08C4 RXIMR17
Base + 0x0888 RXIMR2 Base + 0x08C8 RXIMR18
Base + 0x088C RXIMR3 Base + 0x08CC RXIMR19
Base + 0x0890 RXIMR4 Base + 0x08D0 RXIMR20
Base + 0x0894 RXIMR5 Base + 0x08D4 RXIMR21

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