FlexCAN
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 711
when the module is in Disable mode. Exiting from this mode is done by negating the MDIS bit, which will
resume the clocks and negate the LPM_ACK bit.
18.4.10 Interrupts
The module can generate up to 70 interrupt sources (64 interrupts due to message buffers and 6 interrupts
due to ORed interrupts from MBs, Bus Off, Error, Tx Warning, Rx Warning, and Wake Up). The number
of actual sources depends on the configured number of Message Buffers.
On this device, the individual MB interrupts are grouped as follows:
• Groups of four interrupts (up to MB 16)
• MB16_31
• MB32_63
These are then used as the interrupt source.
Each one of the message buffers can be an interrupt source, if its corresponding mask bit is set. There is
no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer is
initialized for either transmission or reception. Each of the buffers has an assigned flag bit in the IFRL or
IFRH registers. The bit is set when the corresponding buffer completes a successful transmission/reception
and is cleared when the CPU writes a 1 to it (unless another interrupt is generated at the same time).
NOTE
It must be guaranteed that the CPU only clears the bit causing the current
interrupt. For this reason, bit manipulation instructions (BSET) must not be
used to clear interrupt flags. These instructions may cause accidental
clearing of interrupt flags which are set after entering the current interrupt
service routine.
If the Rx FIFO is enabled (bit FEN on MCR set), the interrupts corresponding to MBs 0 to 7 have a
different behavior. Bit 7 of the IFRL becomes the FIFO Overflow flag; bit 6 becomes the FIFO Warning
flag, bit 5 becomes the Frames Available in FIFO flag. and bits 4–0 are unused. See Section 18.3.4.12,
Interrupt Flag Register Low (IFRL), for more information.
A combined interrupt for all MBs is also generated by an OR of all the interrupt sources from MBs. This
interrupt gets generated when any of the MBs generates an interrupt. In this case the CPU must read the
IFRL and IFRH registers to determine which MB caused the interrupt.
The other five interrupt sources (Bus Off, Error, Tx Warning, Rx Warning, and Wake Up) generate
interrupts like the MB ones, and can be read from the Error and Status Register. The Bus Off, Error, Tx
Warning, and Rx Warning interrupt mask bits are located in the Control Register, and the Wake-Up
interrupt mask bit is located in the MCR.
18.4.11 Bus interface
CPU access to FlexCAN registers is subject to the following rules:
• Read and write access to supervisor registers in User mode results in access error.
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