Mode Entry Module (MC_ME)
MPC5606S Microcontroller Reference Manual, Rev. 7
936 Freescale Semiconductor
• From any mode except Reset due to a Safe mode request generated by the MC_RGM because of
some hardware failure in the system (see Chapter 31, Reset Generation Module (MC_RGM), for
details)
As soon as any of the above events has occurred, a Safe mode transition request is generated. The mode
configuration information for this mode is provided by the ME_SAFE_MC register. This mode has a
pre-defined configuration, and the 16MHz int. RC osc. is selected as the system clock. All power domains
are made active in this mode.
If the Safe mode is requested by software while some other mode transition process is ongoing, the new
target mode becomes the Safe mode regardless of other pending requests. In this case, the new mode
request is not interpreted as an invalid request.
NOTE
If software requests to change to the Safe mode and then requests to change
back to the parent mode before the mode transition is completed, the
device’s final mode after mode transition will be the parent mode. However,
this is not recommended software behavior. It is recommended for software
to wait until the S_MTRANS bit is cleared after requesting a change to Safe
before requesting another mode change.
As long as a Safe event is active, the system remains in the Safe mode and no write access is allowed to
the ME_MCTL register.
This mode is intended to be used by software
• To assess the severity of the cause of failure and then to either
— Re-initialize the device via the DRUN mode, or
— Completely reset the device via the Reset mode.
If the outputs of the system I/Os need to be forced to a high impedance state upon entering this mode, the
PDO bit of the ME_SAFE_MC register should be set. In this case, the pads’ power sequence driver cell is
also disabled. The input levels remain unchanged.
NOTE
Peripherals that reside in auxiliary clock domains may be in an unknown
state after exiting the Safe mode to enter the DRUN mode. Therefore
execute a software reset while in the Safe mode if one or more peripherals
present in auxiliary clock domains is required for further operation.
25.4.2.4 Test mode
The device enters this mode on the following events:
• From the DRUN mode when the TARGET_MODE bit field of the ME_MCTL register is written
with “0001”
As soon as any of the above events has occurred, a Test mode transition request is generated. The mode
configuration information for this mode is provided by the ME_TEST_MC register. Except for the main
voltage regulator, all resources of the system are configurable in this mode. The system clock to the whole
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