NXP Semiconductors MPC5606S - Low Frequency Reference Register FMPLL0 (CMU_LFREFR)

Clock Description
MPC5606S Microcontroller Reference Manual, Rev. 7
230 Freescale Semiconductor
8.10.5.4 Low Frequency Reference Register FMPLL0 (CMU_LFREFR)
8.10.5.5 Interrupt Status Register (CMU_ISR)
Offset: 0x0C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0
LFREF[11:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-33. Low Frequency Reference Register FMPLL0
Table 8-32. Low Frequency Reference Register FMPLL0 field descriptions
Field Description
20–31
LFREF
Low Frequency reference value
These bits determine the low reference value for the FMPLL0. The reference value is
given by: (LFREF[11:0]/16) × (FRC
fast
/4).
Offset 0x0010 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0
0
0 FHHI FLLI OLRI
W w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-34. Interrupt Status Register (CMU_ISR)
Table 8-33. Interrupt Status Register (CMU_ISR) field descriptions
Field Description
29
FHHI
FMPLL0 Clock frequency higher than high reference interrupt
This bit is set by hardware when CK_FMPLL frequency becomes higher than HFREF
value and CK_FMPLL is on as signaled by the MC_ME. It can be cleared by software by
writing 1.
0 No FHH event.
1 FHH event is pending.